System Verilog Assertions and Functional Coverage

Guide to Language, Methodology and Applications

Éditeur :

Springer

Paru le : 2019-10-09

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverag...
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Éditeur

Collection
n.c

Parution
2019-10-09

Pages
507 pages

EAN papier
9783030247362

Auteur(s) du livre


Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium design team) and after a route of a couple of startups, worked at Applied Micro and TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs and at TSMC he released two industry standard Reference Flows that establish Reuse of Verification Environment from ESL to RTL. Lately, he has been researching 3DIC design verification challenges at TSMC which is where SystemVerilog Assertions played an instrumental role in stacked die SoC design verification. Ashok earned an MSEE from University of Missouri. He holds 18 U.S. Patents in the field of SoC and 3DIC design verification. 

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EAN PDF
9783030247379
Prix
94,94 €
Nombre pages copiables
5
Nombre pages imprimables
50
Taille du fichier
47534 Ko
EAN EPUB
9783030247379
Prix
94,94 €
Nombre pages copiables
5
Nombre pages imprimables
50
Taille du fichier
158003 Ko

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